View IS41LV8512_343567.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IS41C8512 IS41LV8512
.EATURES

512K x 8 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
Extended Data-Out (EDO) Page Mode access cycle TTL compatible inputs and outputs; tristate I/O Refresh Interval: 1024 cycles /16 ms Refresh Mode: RAS-Only, CAS-before-RAS (CBR), Hidden JEDEC standard pinout Single power supply: 5V 10% (IS41C8512) 3.3V 10% (IS41LV8512) Byte Write and Byte Read operation via CAS Industrail Temperature Range -40oC to 85oC
DESCRIPTION The 1+51 IS41C8512 and IS41LV8512 is a 524,288 x 8-bit
high-performance CMOS Dynamic Random Access Memories. The IS41C8512 offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10 ns per 8-bit. These features make the IS41C8512and IS41LV8512 ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C8512 is packaged in a 28-pin 400mil SOJ and 400mil TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. EDO Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -50 50 14 25 20 90 -60 60 15 30 25 110 Unit ns ns ns ns ns
PIN CON.IGURATIONS 28 Pin SOJ, TSOP-2 PIN DESCRIPTIONS
VCC I/O0 I/O1 I/O2 I/O3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND I/O7 I/O6 I/O5 I/O4 CAS OE NC A8 A7 A6 A5 A4 GND
A0-A9 I/O0-7 WE OE RAS CAS Vcc GND NC
Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
DR008-0B
1
IS41C8512 IS41LV8512
.UNCTIONAL BLOCK DIAGRAM
OE WE CAS CLOCK GENERATOR WE CONTROL LOGICS OE CONTROL LOGIC
CAS
CAS
WE
OE
RAS
RAS CLOCK GENERATOR
DATA I/O BUS
REFRESH COUNTER
DATA I/O BUFFERS
ROW DECODER
RAS
COLUMN DECODERS SENSE AMPLIFIERS
I/O0-I/O7
MEMORY ARRAY 524,288 x 8
ADDRESS BUFFERS A0-A9
TRUTH TABLE
.unction Standby Read Write: Word (Early Write) Read-Write Hidden Refresh RAS-Only Refresh CBR Refresh
Note: 1. EARLY WRITE only.
Read Write(1)
RAS H L L L LHL LHL L HL
CAS H L L L L L H L
WE X H L HL H L X X
OE X L X LH L X X X
Address tR/tC I/O X High-Z ROW/COL DOUT ROW/COL DIN ROW/COL DOUT, DIN ROW/COL DOUT ROW/COL DOUT ROW/NA High-Z X High-Z
2
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
.unctional Description
The IS41C8512 and IS41LV8512 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 10 address bits. These are entered ten bits (A0-A9) at a time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first ten bits and CAS is used the latter nine bits. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 512 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycles falling edge, instead of the rising edge. .or this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.
Power-On Write Cycle
A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first. After application of the VCC supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1024 row addresses (A0 through A9) with RAS at least once every 16 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 10-bit counter provides the row addresses and the external address inputs are ignored.
Integrated Circuit Solution Inc.
DR008-0B
3
IS41C8512 IS41LV8512
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VT VCC IOUT PD TA TSTG Parameters Voltage on Any Pin Relative to GND Supply Voltage Output Current Power Dissipation Commercial Operation Temperature Industrial Operationg Temperature Storage Temperature 5V 3.3V 5V 3.3V Rating 1.0 to +7.0 0.5 to +4.6 1.0 to +7.0 0.5 to +4.6 50 1 0 to +70 40 to +85 55 to +125 Unit V V mA W C C C
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol VCC VIH VIL TA Parameter Supply Voltage Input High Voltage Input Low Voltage Commercial Ambient Temperature Industrial Ambient Temperature 5V 3.3V 5V 3.3V 5V 3.3V Min. 4.5 3.0 2.4 2.0 1.0 0.3 0 40 Typ. 5.0 3.3 Max. 5.5 3.6 VCC + 1.0 VCC + 0.3 0.8 0.8 70 85 Unit V V V C C
CAPACITANCE(1,2)
Symbol CIN1 CIN2 CIO Parameter Input Capacitance: A0-A8 Input Capacitance: RAS, UCAS, LCAS, WE, OE Data Input/Output Capacitance: I/O0-I/O15 Max. 5 7 7 Unit p. p. p.
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz.
4
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.) Symbol IIL IIO VOH VOL ICC1 Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Standby Current: TTL Test Condition Any input 0V < VIN < Vcc Other inputs not under test = 0V Output is disabled (Hi-Z) 0V < VOUT < Vcc IOH = 2.5 mA IOL =+2.1mA RAS, CAS > VIH Commerical Industrial Commerical Industrial 5V 5V 3V 3V 5V 3V -35 -50 -60 -35 -50 -60 -35 -50 -60 -35 -50 -60 Speed Min. 10 10 2.4 Max. 10 10 0.4 3 4 2 3 2 1 230 180 170 220 170 160 230 180 170 230 180 170 Unit A A V V mA
ICC2 ICC3
Standby Current: CMOS Operating Current: Random Read/Write(2,3,4) Average Power Supply Current Operating Current: EDO Page Mode(2,3,4) Average Power Supply Current Refresh Current: RAS-Only(2,3) Average Power Supply Current Refresh Current: CBR(2,3,5) Average Power Supply Current
RAS, CAS > VCC 0.2V RAS, CAS, Address Cycling, tRC = tRC (min.) RAS = VIL, CAS, Cycling tPC = tPC (min.) RAS Cycling, CAS > VIH tRC = tRC (min.) RAS, CAS Cycling tRC = tRC (min.)
mA mA
ICC4
mA
ICC5
mA
ICC6
mA
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tRE. refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR008-0B
5
IS41C8512 IS41LV8512
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) Symbol tRC tRAC tCAC tAA tRAS tRP tCAS tCP tCSH tRCD tASR tRAH tASC tCAH tAR tRAD tRAL tRPC tRSH tCLZ tCRP tOD tOE tOEHC tOEP tOES tRCS tRRH tRCH tWCH tWCR tWP tWPZ tRWL tCWL tWCS tDHR Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(26) CAS Precharge Time(9, 25) CAS Hold Time (21) RAS to CAS Delay Time(10, 20) Row-Address Setup Time Row-Address Hold Time Column-Address Setup Time(20) Column-Address Hold Time(20) Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) Column-Address to RAS Lead Time RAS to CAS Precharge Time RAS Hold Time(27) CAS to Output in Low-Z(15, 29) CAS to RAS Precharge Time(21) Output Disable Time(19, 28, 29) Output Enable Time(15, 16) OE HIGH Hold Time from CAS HIGH OE HIGH Pulse Width OE LOW to CAS HIGH Setup Time Read Command Setup Time(17, 20) Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) Write Command Hold Time (referenced to RAS)(17) Write Command Pulse Width(17) WE Pulse Widths to Disable Outputs Write Command to RAS Lead Time(17) Write Command to CAS Lead Time(17, 21) Write Command Setup Time(14, 17, 20) Data-in Hold Time (referenced to RAS) -35 -50 Min. Max. Min. Max. 60 35 35 20 6 5 35 11 0 6 0 6 30 10 18 0 8 3 5 3 0 10 10 5 0 0 0 5 30 5 10 8 8 0 30 10 18 10K 10K 28 20 12 10 90 50 50 30 8 8 50 19 0 8 0 8 40 14 25 0 14 3 5 3 0 10 10 5 0 0 0 8 40 8 10 14 14 0 40 14 25 10K 10K 36 25 12 15 -60 Min. Max. Units 110 60 40 10 10 60 20 0 10 0 10 40 15 30 0 15 3 5 3 10 10 5 0 0 0 10 50 10 10 15 15 0 40 60 15 30 10K 10K 45 30 12 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.) Symbol tACH tOEH tDS tDH tRWC tRWD tCWD tAWD tPC tRASP tCPA tPRWC tCOH tO.. tWHZ tCLCH tCSR tCHR tORD tRE. tT Parameter Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODI.Y-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODI.Y-WRITE Cycle Time RAS to WE Delay Time during READ-MODI.Y-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time(24) RAS Pulse Width in EDO Page Mode Access Time from CAS Precharge(15) EDO Page Mode READ-WRITE Cycle Time(24) Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) Output Disable Delay from WE Last CAS going LOW to .irst CAS returning HIGH(23) CAS Setup Time (CBR RE.RESH)(30, 20) CAS Hold Time (CBR RE.RESH)(30, 21) OE Setup Time prior to RAS during HIDDEN RE.RESH Cycle Refresh Period (1024 Cycles) Transition Time (Rise or .all)(2, 3) -35 Min. Max. 15 8 0 6 80 45 25 30 12 35 40 5 3 3 10 8 8 0 1 100K 21 15 15 16 50 -50 Min. Max. 15 8 0 6 100 50 30 30 15 40 45 5 3 3 10 10 10 0 16 1 100K 27 15 15 50 -60 Min. Max. 15 15 0 10 140 80 36 49 25 50 56 5 3 3 10 10 10 0 16 1 100K 34 15 15 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns
Integrated Circuit Solution Inc.
DR008-0B
7
IS41C8512 IS41LV8512
Notes: 1. An initial pause of 200 s is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tRE. refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 p.. 7. Assumes that tRCD tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tO.. (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODI.Y-WRITE cycle only. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODI.Y-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODI.Y-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tO.. occur. 20. The first CAS edge to transition LOW. 21. The last CAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODI.Y-WRITE cycles. 23. Last falling CAS edge to first rising CAS edge. 24. Last rising CAS edge to next cycles last rising CAS edge. 25. Last rising CAS edge to first falling CAS edge. 26. Each CAS must meet minimum pulse width. 27. Last CAS to go LOW. 28. I/Os controlled, regardless CAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters.
8
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
READ CYCLE
tRC tRAS tRP
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH tRRH
CAS
tAR tASR tRAD tRAH tRAL tASC tCAH
ADDRESS WE
Row
tRCS
Column
tRCH
Row
tAA tRAC tCAC tCLC
tOFF(1)
I/O
Open
tOE
Valid Data
tOD
Open
OE
tOES
Undefined Don't Care
Note: 1. tO.. is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR008-0B
9
IS41C8512 IS41LV8512
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC tRAS tRP
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
CAS
tAR tASR tRAD tRAH tASC tRAL tCAH tACH
ADDRESS
Row
Column
tCWL tRWL tWCR tWCS tWCH tWP
Row
WE
tDHR tDS tDH
I/O
Valid Data
Don't Care
10
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
READ WRITE CYCLE (LATE WRITE and READ-MODI.Y-WRITE Cycles)
tRWC tRAS
tRP
RAS
tCSH tCRP tRCD tRSH tCAS tCLCH
CAS
tAR tASR tRAD tRAH tRAL tASC tCAH tACH
ADDRESS
Row
tRCS
Column
tRWD tCWD tAWD
Row
tCWL tRWL tWP
WE
tAA tRAC tCAC tCLZ tDS tDH
I/O
Open
tOE
Valid DOUT
tOD
Valid DIN
Open
tOEH
OE
Undefined Don't Care
Integrated Circuit Solution Inc.
DR008-0B
11
IS41C8512 IS41LV8512
EDO-PAGE-MODE READ CYCLE
tRASP tRP
RAS
tCSH tCRP tRCD tCAS, tCLCH tCP tPC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP
CAS
tAR tRAD tASR tASC tCAH tASC tCAH tASC tRAL tCAH
ADDRESS
Row
tRAH tRCS
Column
Column
Column
tRCH
Row
tRRH
WE
tAA tRAC tCAC tCLZ tCAC tCOH tAA tCPA tCAC tCLZ tAA tCPA tOFF
I/O
Open
tOE tOES
Valid Data
Valid Data
tOEHC tOD tOES
Valid Data
tOE
Open
tOD
OE
tOEP
Undefined Don't Care
Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
12
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP tRP
RAS
tCSH tCRP tRCD tCAS, tCLCH tCP tPC tCAS, tCLCH tCP tRSH tCAS, tCLCH tACH tRAL tCAH tCP
CAS
tAR tRAD tASR tASC tACH tCAH tASC tACH tCAH tASC
ADDRESS
Row
tRAH
Column
tCWL tWCS tWCH tWP
Column
tCWL tWCS tWCH tWP
Column
tCWL tWCS tWCH tWP
Row
WE
tWCR tDHR tDS tDH tRWL tDS tDH tDS tDH
I/O OE
Valid Data
Valid Data
Valid Data
Don't Care
Integrated Circuit Solution Inc.
DR008-0B
13
IS41C8512 IS41LV8512
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODI.Y WRITE Cycles)
tRASP tRP
RAS
tCSH tCRP tRCD tCAS, tCLCH tCP tPC / tPRWC(1) tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP
CAS
tASR tRAH tAR tRAD tASC tRAL tCAH
tCAH
tASC
tCAH
tASC
ADDRESS
Row
tRWD tRCS
Column
tCWL tWP tAWD tCWD
Column
tCWL tWP tAWD tCWD
Column
tRWL tCWL tWP tAWD tCWD
Row
WE
tAA tRAC tCAC tCLZ tDH tDS tAA tCPA tCAC tCLZ tDH tDS tAA tCPA tCAC tCLZ tDH tDS
I/O
Open
tOE
DOUT
DIN
tOD tOE
DOUT
DIN
tOD tOE
DOUT
DIN
tOD tOEH
Open
OE
Undefined Don't Care
Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications.
14
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODI.Y WRITE)
tRASP
tRP
RAS
tCSH tPC tCRP tRCD tCAS tCP tCAS tPC tCP tRSH tCAS tCP
CAS
tASR tRAH tAR tRAD tASC tACH tRAL tCAH
tCAH
tASC
tCAH
tASC
ADDRESS
Row
tRCS
Column (A)
Column (B)
tRCH tWCS
Column (N)
tWCH
Row
WE
tAA tRAC tCAC tCPA tCAC tCOH tAA tWHZ tDS tDH
I/O
Open
tOE
Valid Data (A)
Valid Data (B)
DIN
Open
OE
Don't Care
Integrated Circuit Solution Inc.
DR008-0B
15
IS41C8512 IS41LV8512
AC WAVE.ORMS READ CYCLE (With WE-Controlled Disable)
RAS
tCSH tCRP tRCD tCAS tCP
CAS
tAR tASR tRAD tRAH tASC tCAH tASC
ADDRESS WE
Row
tRCS
Column
tRCH tRCS
Column
tAA tRAC tCAC tCLZ
tWHZ
tCLZ
I/O
Open
tOE
Valid Data
Open
tOD
OE
Undefined Don't Care
4)5-ONLY RE.RESH CYCLE (OE, WE = DON'T CARE) 4)5
tRC tRAS tRP
RAS
tCRP tRPC
CAS
tASR tRAH
ADDRESS I/O
Row Open
Row
Don't Care
16
Integrated Circuit Solution Inc.
DR008-0B
IS41C8512 IS41LV8512
+*4 RE.RESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tRPC tCP tCHR tCSR tRPC tCSR tCHR
CAS I/O Open
HIDDEN RE.RESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS tRP tRAS
RAS
tCRP tRCD tRSH tCHR
CAS
tAR tASR tRAD tRAH tASC tRAL tCAH
ADDRESS
Row
Column
tAA tRAC tCAC tCLZ tOFF(2)
I/O
Open
tOE tORD
Valid Data
Open
tOD
OE
Undefined Don't Care
Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tO.. is referenced from rising edge of RAS or CAS, whichever occurs last.
Integrated Circuit Solution Inc.
DR008-0B
17
IS41C8512 IS41LV8512
ORDERING IN.ORMATION IS41C8512 Commercial Range: 0C to 70C
Speed (ns) Order Part No. 35 50 60 IS41C8512-35K IS41C8512-35T IS41C8512-50K IS41C8512-50T IS41C8512-60K IS41C8512-60T Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
ORDERING IN.ORMATION: IS41LV8512 Commercial Range: 0C to 70C
Speed (ns) Order Part No. 35 50 60 IS41LV8512-35K IS41LV8512-35T IS41LV8512-50K IS41LV8512-50T IS41LV8512-60K IS41LV8512-60T Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
Industrial Range: -40C to 85C
Speed (ns) Order Part No. 35 50 60 IS41C8512-35KI IS41C8512-35TI IS41C8512-50KI IS41C8512-50TI IS41C8512-60KI IS41C8512-60TI Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
Industrial Range: -40C to 85C
Speed (ns) Order Part No. 35 50 60 IS41LV8512-35K IS41LV8512-35T IS41LV8512-50KI IS41LV8512-50TI IS41LV8512-60KI IS41LV8512-60TI Package 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2 400mil SOJ 400mil TSOP-2
HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 .ax: 886-3-5783000 BRANCH O..ICE: 7., NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 .AX: 886-2-26962252 http://www.icsi.com.tw
18 Integrated Circuit Solution Inc.
DR008-0B
Integrated Circuit Solution Inc.

▲Up To Search▲

Price & Availability of IS41LV8512

	To Download IS41LV8512 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .